Related fields include atomic layer deposition, high-performance logic, and mitigation of native-oxide effects on semiconductor device performance.
Traditional device scaling of logic devices based on silicon (Si) has encountered obstacles. Inherent material properties have placed limitations on further miniaturization, increases in processing speed, and other performance enhancements. For example, as gate conductor width decreases, gate dielectric thickness also needs to decrease to provide sufficient capacitance to control the transistor. Suppression of leakage current is critical to performance of a capacitor dielectric. Silicon oxide layers <2 nm thick are subject to unacceptably high leakage current due to tunneling effects.
Tunneling leakage decreases as a function of physical thickness. Therefore, there has been interest in gate dielectric materials that would exhibit the same capacitance as 1-2 nm thick silicon dioxide (SiO2) at a physical thickness too large for significant tunneling leakage (e.g., >=5 nm). Metal oxides with high dielectric constants (“high-k materials”) such as hafnium oxide (HfOx), aluminum oxide (Al2O3), and zirconium oxide (ZrOx) are, among others, being investigated as gate-dielectric candidates to replace silicon oxide.
Another avenue of exploration is replacement of Si channels with higher-mobility, lower-effective-mass materials such as germanium (Ge). Ge and Si—Ge are being explored for surface channels and strained buried channels. Indium gallium arsenide (InGaAs) is another Si substitute under consideration. The new materials, however, face various integration challenges. Several of these challenges are rooted in the susceptibility of these materials to growth of unstable native oxides that increase operational power consumption and decrease reliability.
Uncontrolled native oxide growth under a capacitor dielectric can unpredictably affect the effective oxide thickness (EOT=(kSiO2/k)t) and the capacitive effective thickness (CET˜EOT+(kSiO2/k)zavg for an ultra-thin gate dielectric) of a logic stack. In the equations, k=dielectric constant of the actual material, t=physical thickness of the actual material, Zavg=average distance of inversion carriers from the gate-dielectric interface, and kSiO2=dielectric constant of SiO2˜3.9.
Removing the native oxide from Ge immediately before atomic layer deposition (ALD) of a high-k metal oxide layer has proven to be an incomplete solution. Although the ambient air that often triggers native GeOx growth is excluded from the ALD process chamber, the oxygen precursors (e.g., H2O) used for the high-k layer deposition can encourage the native GeOx to regrow. Some of the high-k materials, such as Al2O3 and HfOx, are permeable in thicknesses less than about 25 angstroms (Å). Unbonded oxygen or oxidant molecules can diffuse through the high-k layers and grow native GeOx underneath them even after they are partially (or, in some cases, fully) deposited.
Therefore, advanced logic technology would benefit if the unwanted dielectric effects of unstable native-oxide growth in materials such as Ge and InGaAs could be mitigated. In particular, a treatment that could work through permeable overlying layers would be desirable.